1. Field of the Invention
The present invention relates to a method for fabricating a non-volatile memory device, and more particularly to a method for fabricating a NAND type flash memory device.
2. Discussion of Related Art
Among the several types of read-only memory (ROM) devices, a flash memory device, a type of non-volatile EEPROM (Electrically Erasable & Programmable Read Only Memory) device, is widely used for computers, digital still cameras and similar devices.
Flash memory devices can be of two types, namely, a NOR type and a NAND type. The NOR type flash memory device is not readily applicable to realization in high integration because one contact is required for every two cells. However, the NOR type flash memory device is typically faster than a NAND type flash memory device and is therefore more suitable for high-speed operation. On the contrary, the NAND type flash memory device can be densely integrated on a chip because a plurality of cells share one contact. Therefore, the NAND type flash memory device is receiving considerable attention for use in the next generation memory.
FIGS. 1 through 3 illustrate a conventional method for fabricating a NAND type flash memory. Referring to FIG. 1, gate patterns 20 are formed on a semiconductor substrate on which a gate oxide layer 12 is formed. The gate patterns 20 are formed by sequentially stacking a first polysilicon layer 14 used as a floating gate, a dielectric layer 16, a second polysilicon layer 18 used for a control gate, a silicide layer 22, and a gate insulating layer 24.
Referring to FIG. 2, a capping layer 26 made of an nitride layer is deposited on the whole surface of the semiconductor substrate 10 on which the gate patterns 20 are formed. Then, an interlayer insulating layer 28 made of an oxide layer is thickly deposited so as to fill the gap between the gate patterns 20, and is planarized by Chemical Mechanical Polishing (CMP) process. The CMP process of the interlayer insulating layer 28 is performed until the surface of the capping layer 26 is exposed to act as a blocking layer.
Referring to FIG. 3, a common source line (CSL) 30 for commonly connecting a plurality of bit lines to a source is formed between the gate patterns 20. To form the CSL 30, after removing a part of the interlayer insulating layer 28, the capping layer 26 and the gate oxide layer 12 in order between the gate patterns 20, a conductive material is deposited on the insulating layer 28 and to fill the removed part. Then, the conductive material is planarized by a second CMP process until the surface of the interlayer insulating layer 28 is exposed.
According to the above conventional method, the fabrication process for a NAND type flash memory requires repeated CMP processes (i.e., twice) to form the CSL 30. Furthermore, after the interlayer insulating layer 28 is planarized by CMP, the height of the interlayer insulating layer is still high because the gate pattern 20 includes the silicide layer 22.